The success of nearly every multichip electronic system depends on the availability of functional, reliable integrated circuit ("IC") chips. As chip counts in a multichip system increase, this dependency is critical. In most cases, "known good die" ("CKGD") are not readily available in an unpackaged form. The definition of KGD is a bare die that has the performance and warranty from the supplier of a conventionally packaged and tested die.
Most manufacturers of multichip electronic modules ("MCM") require high yield and reliable IC chips to avoid low yields and reliability at the assembly level. High chip yield translates into an availability to full speed test ("FST") and burn-in ("B/I") singular, bare ICs before they are committed to an electronic assembly. Many IC's have potential defects which can only be detected when the chip is operating at speeds (clock speeds and input/output speeds) similar to that of actual use. Full speed testing under these conditions requires more sophisticated testing equipment and connection techniques compared to conventional wafer probing technology. "Burn-in" refers to the testing of an item in a process in order to stabilize that item's characteristics. FST and B/I are advantageous when IC yields are low, and/or when conventional type IC testing is an inadequate screen for faulty ICs. Conventional IC probing has consisted merely of DC (direct current) probing which cannot fully test an IC being prepared for assembly technology such as flip-chip and wire-bonding. (A "flip-chip" is a semi-conductor chip with thickened and extended bonding pads enabling it to be flipped over and mounted upside down on a suitable substrate. "Wire bonding" is a method used during the packaging of ICs to connect the chip to the leadframe.) Furthermore, wire probe technologies can only test chips fabricated with a.gtoreq.6 mil pitch. Membrane probe technologies provide a partial answer to IC FST at the wafer level, however, membrane probes cannot perform IC burn-in. Also, membrane probes do not address warranting the bare IC device when being shipped from the IC vendor to the end assembly house. Even with packaged IC devices, considerable precautions are taken to prevent damage to the device between the time it is tested and the time the customer assembles it into a system. These precautions include conductive foam and shielded bags to prevent electrostatic discharge damage, packaging to prevent mechanical damage, etc. With bare IC's the problems are compounded.
Users that benefit from an ability to perform FST and B/I on singular, bare ICs are mostly electronic systems manufacturers with relatively little vertical integration, who are involved in advanced packaging (MCM) efforts. In most cases, these users' current bare-chip usage is not sufficient to influence their chip suppliers to perform additional processes. Furthermore, they are often unable to procure their chips in whole wafer form, because their supplier considers wafer yields to be proprietary information.
As a result of the foregoing, there is a need for a technique suitable for single chip dynamic burn-in and high speed testing (including elevated temperature testing), which is implementable by a bare die user with existing commercial technology and is compatible with low-to-medium volume production. Non-recurring engineering and tooling costs should be kept as low as possible.